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Prior to Imperas, Peter was a Scientist at Synopsys where he participated in the definition of SystemVerilog 3.1 and 3.1A and co-authored the SystemVerilog for Design book. Before its acquisition by Synopsys, at Co-Design Automation he was the CTO and lead architect of the Superlog language which became SystemVerilog. As an Architect at Cadence Design Systems Peter developed Verilog simulators and behavioral synthesis tools. At Brunel University, and GenRad, Inc., Peter was the language architect and technical leader of the HILO project. HILO-2 became the first commercial and a very successful HDL based simulation, fault simulation, and timing analysis system. Peter has a Masters degree from Cambridge University, U.K. | 