Jose Maiz is an Intel Fellow and director of Logic Technology Quality and Reliability. He joined Intel in 1983, and was promoted to fellow in 2002. He is presently responsible for identification of silicon reliability limiters to scaling, and their resolution for Intel's next generation silicon technologies and logic products.
He first joined Intel's 1Mbit DRAM program transitioning to the 1µm logic technology generation. He has since led silicon reliability teams at various phases of development, including the ramp readiness of the 180nm technology generation. Since the mid 80's, he has been a major force in integrating technology reliability with technology development to ensure that Intel's logic processes are robust for reliability while delivering top performance. He has originated or developed many innovative Quality and Reliability methodologies, including Electromigration under non-direct currents and on short lines, use of SCRs and specially designed transistors for Electrostatic Damage protection, risk assessment methodologies, use conditions to assess reliability risk, improvement of electromigration capabilities for copper, and inter-leaving rules to protect memories against soft errors, among others. He is presently focused on the 45nm technology.
Maiz holds 4 patents and has 10 more pending. He has authored or co-authored over 25 publications and conference presentations, a number of them invited. He is presently co-editor of a special issue of IEEE Transactions in Device and Materials Reliability focused on soft errors.
He is a co-recipient of an Intel Achievement award for the "Development of a complete solution for ESD protection on logic technologies using standard cells" in 1991 and has received numerous divisional recognition awards. He is also a Fulbright Scholar (1978). Jose Maiz was born in San Sebastian, Spain, in 1954. He graduated with a degree in physics from the University of Navarra in San Sebastian in 1976. He then moved to the U.S., graduating with a master of science and a Ph.D in Electrical Engineering from Ohio State University in 1980 and 1983 respectively.
He presently chairs the committee overseeing Intel's university research in reliability as well as interconnect processing. He has served in the past as Intel's reliability representative in the Sematech RTAB, served in paper selection committees for the International Reliability Physics Symposium (IRPS) and International Electron Devices Meeting (IEDM), chaired workshops like the 2002 Topical Research Conference on Reliability and the 2002 IRPS workshop on Soft Errors. He also serves in the CEIT Research Institute advisory board.