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Joe Rahmeh, cofounder and engineering fellow, has over 15 years of experience in EDA tool development at SUN Microsystems, Monterey Design, and as a consultant to IBM’s PowerPC design team. He has been a key architect and developer of static timing analysis, noise analysis, clock tree synthesis, test pattern generation, and simulation tools for system level performance modeling. Prior to his career in EDA tool development, Joe spent four years as an Assistant Professor at the University of Texas in Austin, where he taught graduate and undergraduate courses in the electrical engineering department. During that time he supervised graduate research in the areas of computer architecture and computer aided design. Joe has a Ph.D. in Electrical Engineering from the University of Illinois. He has authored over thirty technical papers in the CAD area. | 